module pc (R, Incr, Rin, Clock, Q);
	parameter n = 8;
	input [n:0] R;
	input Incr, Rin, Clock;
	output reg [n:0] Q;
	
	initial begin
		Q <= 0;
	end
	
	always @(posedge Clock) begin
		if (Rin == 1)
			Q <= R;
		if (Incr == 1)
			Q <= Q + 8'b00000001;
	end
endmodule
